This present invention relates to digital interface circuitry. More specifically, it relates to voltage level shifters.
As digital circuitry and systems have evolved, they have been designed to utilize steadily lower supply voltage levels. For example, early Transistor-Transistor-Logic (TTL) digital logic circuits typically operated from a 5 volt (V) power supply. As the need for power efficiency has grown, primarily with respect to mobile devices, the typical power supply voltage for devices dropped to 3V and, now, devices designed to operate from 1.8V supply levels dominate the market. Also, as the transistor geometries for integrated circuit technology have dropped, some devices are unable to operate using higher voltage supply levels. Further, lower voltage levels reduce output voltage swings and, consequently, the noise produced by the circuit.
However, many architectural standards, such as bus standards, were developed when a different logical voltage level was the norm. Also, systems may incorporate devices having different supply voltage requirements. For example, a system may include a processor, memory controller and memory that are designed to operate using 1.8V, while the system bus may be designed to operate using 3.3V of have come to operate traditionally. For example, the Peripheral Control Interface (PCI) Local Bus is designed to operate using 5V and 3.3V signaling levels. See the PCI Local Bus Specification version 2.2, herein incorporated in its entirety for all purposes.
FIG. 1 illustrates an example of a system architecture 10 utilizing a PCI local bus 40. A microprocessor 20 directly interfaces to a cache 22 and memory controller 30 via the processor bus. Memory controller 30 also interfaces to a dynamic random access memory (DRAM) device 32 and to PCI local bus 40. The memory controller 30 provides a bridge to the PCI bus from the processor bus and handles access to DRAM 32 and the other devices coupled to PCI local bus 40 for the processor 20. Architecture 10 includes a representative selection of peripheral devices, e.g. network interface 42 for communications with an external network such as a local area network (LAN), graphics interface 44 for driving a video output, peripheral interface 46 for interfacing to other peripheral devices, such as keyboards, modems, etc., and disk controller 50 for controlling bulk storage to disk 52.
Today, processor 20, cache 22, memory controller 30 and DRAM 32 are often designed for use with a 1.8V supply. However, as noted above, the PCI standard currently calls for logic signaling levels based on 3.3V or 5V. This raises the problem of interfacing between devices operating using different supply levels. For example, interfacing the output from a higher voltage device, such as a 5V device, to the input of a lower voltage device, such as a 3.3V device, can forward bias the Electrostatic Discharge (ESD) protection diode typically coupled to the input pad.
Systems may incorporate devices operating from a variety of supply sources having different levels. FIG. 2 is a diagram of a clock generation architecture 60 wherein a system clock source 80 operating from voltage supply VDDIR, e.g. 3V, produces a reference clock signal RefCLK that is input to a Direct Rambus Clock Generator (DRCG) circuit operating from another voltage supply VDD, e.g. 1.8V, and producing a Bus Clock signal based on another supply voltage VDDIPD. The Bus Clock, in turn, drives Rambus DRAMs (RDRAM) 92 and 94, which are controlled by memory controller 90. The Rambus DRCG 70, controller 90, and RDRAMs 92 and 94 operate using the Rambus Signal Level (RSL), wherein a logic xe2x80x981xe2x80x99 is represented by 1.0V and a logic xe2x80x980xe2x80x99 is represented by 1.8V, which is the Rambus supply voltage. See Direct Rambus Clock Generator, Document DL-0056, Version 1.2, Rambus Inc., November 2000, herein incorporated in its entirety for all purposes.
In order to allow an output operating from one voltage level to drive an input operating from a lower voltage level, an input level translator is typically required. FIG. 3 illustrates one example of an input level translator relating to the clock generation architecture 60 of FIG. 2. An output pin of clock source 80 includes an output driver 82 that operates from the supply voltage VDDIR, which typically ranges from 1.3V to 3.3V. The output signal from output driver 82 reflects the voltage level of VDDIR, The output driver 82 drives an input pin of DRCG 70, which includes an input comparator 72 that operates from supply voltage VDDIPD. DRCG 70 also has an input that receives VDDIR, which is divided by resistors 74 and 76 to obtain a threshold voltage that is input to comparator 72. Comparator 72 compares the voltage signal received from output driver 82 with the threshold voltage obtained by dividing VDDIR in order to generate a received signal having logic voltage levels that reflect the voltage level VDDIPD.
Conventional input level shifters appear in a variety of forms, such as operational amp lifier network, resistive divider network, or source follower . FIG. 3 illustrates an example of a combination resistive divider and operation amplifier, where comparator 72 is implemented as an operational amplifier. FIG. 4 illustrates an example of a source follower input circuit 100 composed of transistor 102, input resistor 104 and source resistor 106. In source follower circuit 100, a higher voltage signal received at DIN is reflected at the source of transistor 102, which is coupled to DOUT. The voltage levels appearing at DOUT are determined by the magnitude of supply voltage VDDI coupled to the d rain of transistor 102. A variety of conventional level shifter circuits are shown in U.S. Pat. Nos. 6,160,421; 6,097,215; 5,986,472; 5,973,508; 5,867,010; 5,757,712, 5,751,168; 5,663,663; 5,534,798; and 5,534,795, herein incorporated by reference for all purposes.
Conventional level shifters have a limited ability to shift from an external voltage level to an internal voltage level. Source follower circuits are dependent on the threshold voltage Vt of the transistor and tolerate only a narrow range between the external voltage level and the internal supply voltage. (?)Consequently, the source follower circuits must be tuned to each particular application. In addition, source followers do not provide gain for the input signal. In resistive divider circuits, the ratio of the resistors must be selected for the relationship between the external and internal voltage sources for the particular application and, as a result, cannot tolerate much variation in the external supply voltage. Also, the introduction of resistance to the receive path will slow the response of the input circuit making resistive dividers unsuitable for high speed applications.
Operational amplifier based circuits can be configured to introduce gain to the input signal path. However, the gain of the operation amplifier is determined by the ratio of the feedback resistance to the input resistance for the amplifier. This ratio is fixed and must be designed for a specific ratio of external to internal voltage levels. The resistance also tends to slow the circuit, resulting in poor high speed performance. For a differential input amplifier circuit, transistors must generally be stacked and a low internal voltage supply level, e.g. VDD less than 2Vt, the differential pair of the amplifier will run out of headroom to operate. In other words, the supply voltage level becomes insufficient to accommodate the output swing of the circuit without introducing distortion. For a single-ended input amplifier circuit, the gain offset can become quite large because the current source for the circuit may be pushed into its linear operating region. This causes distortion of the output signal for the receiver, such as duty cycle error. This occurs because there is a higher gain level when the data signal is higher, but lower gain when the reference voltage for the circuit is higher, since the reference voltage is less than the peak amplitude of the data
FIG. 5 is a waveform diagram illustrating an example of the distortion that can occur due to a lack of operating headroom in a conventional receiver that utilizes a source follower to perform level shifting. In FIG. 5, waveform 110 represents a reference voltage for an input data signal represented by waveform 112. In this example, reference voltage 110 is approximately 1.4V and data signal 112 varies from 1V to 1.8. Likewise, waveform 114 represents a level shifted reference voltage for a level-shifted data signal 116 that results from the level shifting of data signal 112. Waveforn 120 represents the output voltage waveform of a gain stage that results from the input data signal 112 after it has been level shifted and amplified in a circuit having inadequate headroom.
Waveform 120 exhibits distortion due to voltage undershoot (illustrated at 122) and a flattening of the waveform (illustrated at 124) due to lack of headroom in the circuit. Further, waveform 120 exhibits an offset error (illustrated at 126), where the output waveform has become offset in time from the input waveform. Note that the troughs and peaks of waveform 120 are not centered between the vertical time intervals, as are those of waveform 112, but are offset to the right of center. This offset arises because of the time delay through a level-shift or gain stage portion of the input circuit. Further note that the slopes of the rising and falling portions of waveform 120 are different. This difference between the slopes also gives rise to distortion and errors in the output signal.
Thus, the need remains for an input circuit that operates at low supply voltage levels and is also capable of level shifting higher voltage input signals without introducing significant distortion.
An embodiment of a level-shifting input receiver circuit, according to the present invention, includes a differential amplifier having first and second input terminals, first and second output terminals, and first and second power terminals. The first input terminal of the differential amplifier is configured to receive an input data signal, the second input terminal is configured to receive a reference signal, and the first power terminal is configured to receive a first power supply voltage. The receiver circuit also includes a first current source having a first power terminal coupled to the second power terminal of the differential amplifier, a second power terminal configured to receive a second power supply voltage, and a control terminal configured to receive a bias control signal. The differential amplifier drives a first load having a first terminal configured to receive a third power supply voltage and a second terminal coupled to the first output terminal of the differential amplifier. Further included is a second current source having a first power terminal coupled to the first output terminal of the differential amplifier, a second power terminal configured to receive the second power supply voltage, and a control terminal configured to receive the bias control signal. Also provided is a second load having a first terminal configured to receive the third power supply voltage and a second terminal coupled to the second output terminal of the differential amplifier. Finally, there is a third current source having a first power terminal coupled to the second output terminal of the differential amplifier, a second power terminal configured to receive the second power supply voltage, and a control terminal configured to receive the bias control signal. A further refinement of this embodiment of a receiver circuit includes a first clamp circuit configured to shunt current between the first output terminal of the differential amplifier and the second power supply voltage and a second clamp circuit configured to shunt current between the second output terminal of the differential amplifier and the second power supply voltage.
An embodiment of a method for level-shifting a received signal, according to the present invention, calls for receiving an input signal having logic levels related to an external power supply voltage, receiving a reference voltage configured to differentiate between the logic levels of the received input signal, and differentially comparing the received input signal and the received reference voltage to generate a differential current signal, where the differential current signal is sourced from the external power supply voltage. The method further recites coupling a resistive load in series with a pulling current source between an internal power supply voltage and a ground supply voltage and driving the resistive load with the differential current signal. A further refinement of this embodiment of the present invention calls for clamping the differential current signal to the ground supply voltage.
An embodiment of an apparatus for level-shifting a signal, according to the present invention, includes an external power supply terminal, an internal power supply terminal, a ground supply terminal, a data input terminal, a reference input terminal, and a bias input terminal. The apparatus also includes first, second and third current sources, each of the first, second and third current sources having first and second current terminals and a control terminal. Each of the first, second and third current sources is configured to conduct current between the first to the second current terminals under control of a signal received at the control terminal. The second current terminal of each of the first, second and third current sources is coupled to the ground supply terminal. The control terminal of each of the first, second and third current sources is coupled to the bias input terminal. A differential input buffer of the apparatus has a first input node coupled to the data input terminal, a second input node coupled to the reference input terminal, a first power node coupled to the external power supply terminal, a second power node coupled to the first current terminal of the first current source, a first output terminal coupled to the first current terminal of the second current source, and a second output terminal coupled to the first current terminal of the third current source. A first resistive load is coupled between the internal power supply terminal and the first output terminal of the differential input buffer. Finally, a second resistive load is coupled between the internal power supply terminal and the second output terminal of the differential input buffer. A further refinement of this embodiment of an apparatus according to the present invention includes a clamp circuit having a first current terminal coupled to the first output terminal of the differential input buffer and a second current terminal coupled to the second output terminal of the differential input buffer, and a third current terminal coupled to the ground supply terminal, where the clamp circuit is configured to sink current from one of the first and second current terminals of the clamp circuit to the third current terminal of the clamp circuit responsive to the voltage at one of the first and second current terminals of the clamp circuit exceeding a predetermined voltage level.
The foregoing and other features and advantages of the system and method for level-shifting will be more apparent from the following description of embodiments of the system and method as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. dr
Preferred embodiments of the present inventions are described with reference to the following drawings, wherein:
FIG. 1 is a functional block diagram illustrating an example of a system architecture employing devices that may operate with a variety of logic voltage levels and power supply levels;
FIG. 2 is a functional block diagram illustrating another example of a system architecture employing devices that may operate with a variety of logic voltage levels and power supply levels;
FIG. 3 is a circuit diagram illustrating an example of a conventional level-shifting input receiver circuit configured to receive a signal from an output driver circuit operating using a different power supply voltage level and logic voltage level from that of the receiver circuit;
FIG. 4 is a circuit diagram illustrating another example of a conventional level-shifting input receiver circuit configured to receive a signal from an output driver circuit operating using a different power supply voltage level and logic voltage level from that of the receiver circuit;
FIG. 5 is a waveform diagram illustrating an input data signal, intermediate circuit node signals, and the distortion that may be introduced to a resulting output signal by a conventional level-shifting input receiver circuit;
FIG. 6 is a functional block diagram illustrating an embodiment of a level-shifting input receiver circuit, according to the present invention, configured to receive a signal from an output driver circuit operating using a different power supply voltage level and logic voltage level from that of the receiver circuit;
FIG. 7 is a waveform diagram illustrating an example of an input data signal, intermediate circuit gain node signals, and a resulting output signal produced by the level-shifting input receiver circuit of FIG. 6; and
FIG. 8 is a circuit diagram illustrating, at a transistor level, an embodiment of a level-shifting input receiver circuit, according to the present invention, that includes optional clamping circuitry.